Hanieh Totonchi Asl, Ebrahim Nouri, Zhuoran Li, Danella Zhao · 2026 · arXiv (Cornell University)
DOI: 10.48550/arxiv.2610.27431 · cited by 0 works (OpenAlex) · open-access PDF
通过PPML(Privacy-preserving machine learning)提供了一个有希望的路径,将强大的AI服务带到边缘,而不会暴露敏感的用户数据。然而,其实际部署仍然受到安全多方计算(MPC)的高通信、计算和数据移动成本的限制,尤其是在非线性推断过程中。现有的MPC系统通常会将输入独立的随机发生率生成从在线执行中解除,从而产生大量的内存压力,以缓冲单次使用的加密数据。此外,有限的存储可以强迫一个停止和填补的执行模式,这在非线性推断过程中反复阻止管道补充这些缓冲器,从而将随机发生率带回关键路径。我们建议Interflow,一个基本硬件共同设计的记忆器,通过组合式处理和改进
Machine translation (Meta M2M100); the English original follows.
Privacy-preserving machine learning (PPML) offers a promising path toward bringing powerful AI services to the edge without exposing sensitive user data. However, its practical deployment remains constrained by the high communication, computation, and data-movement costs of secure multi-party computation (MPC), particularly during nonlinear inference. Existing MPC systems typically decouple input-independent correlated randomness generation from online execution, creating substantial memory pressure to buffer single-use cryptographic data. Moreover, limited storage can force a stop-and-refill execution pattern that repeatedly stalls the pipeline to replenish these buffers, bringing randomness generation back onto the critical path. We propose Interflow, an algorithm-hardware co-design that rethinks this separation by batch-wise processing and pipelining correlated-randomness generation with online execution: while the current batch consumes pre-generated randomness to execute secure nonlinear operations, correlation generation proceeds concurrently for the next batch. By leveraging interleaved execution, efficient data movement, and hardware acceleration, the design transforms preprocessing from a serialized, storage-intensive offline phase into a continuously overlapped pipeline that generates correlated randomness closer to the point of consumption, reducing memory footprint and data movement overhead. Implemented on the Zynq UltraScale+ ZCU102, Interflow improves nonlinear evaluation throughput by up to 1.55x for CNN operators and 1.48x for transformer operators. It achieves up to 1.26x speedup for ResNet-50 and up to 1.21x speedup for BERT-base, and reduces memory footprint by up to 37%, compared with baseline frameworks.
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Topics: Computer science, Speedup, Randomness, Pipeline (software), Memory footprint, Throughput
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