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Evaluating the Applicability of LLM Inference Optimizations on Apple Silicon

Kyrylo Yemets, Andrii Yaroshevych, Victor Muryn, Ostap Khomenko, Pavlo Kryven, Maksym Kmet, Maksym Shamrai, Mariya Hirna · 2026 · arXiv (Cornell University)

DOI: 10.48550/arxiv.2610.31479 · cited by 0 works (OpenAlex) · open-access PDF

Russian

Apple Silicon является одной из наиболее широко используемых платформ для локального вывода LLM, но почти все оптимизации вывода разработаны и подтверждены на GPU сервера класса NVIDIA под отгруженными рабочими нагрузками. Какие оптимизации сохраняют свои преимущества при переходе на Apple Silicon, и что определяет их применимость? Мы оцениваем четыре семейства оптимизации: KV-cache pruning, спекулятивное декодирование, портативные GPU-ядра и пост-тренировочную квантизацию. Эксперименты охватывают четыре машины Apple под общим однозапросным декодированием рабочей нагрузки, с сопоставимыми RTX 4090 сравнениями, где это возможно. KV-cache pruning может достигать до 1,75 раз конечного конечного производства через Apple, но

Machine translation (Meta M2M100); the English original follows.

Abstract

Apple Silicon is among the most widely used platforms for local LLM inference, yet nearly all inference optimizations are designed and validated on server-class NVIDIA GPUs under batched serving workloads. Which optimizations retain their benefits when moved to Apple Silicon, and what determines their applicability? We evaluate four optimization families: KV-cache pruning, speculative decoding, ported GPU kernels, and post-training quantization. Experiments span four Apple machines under a common single-request decode workload, with matched RTX 4090 comparisons where possible. KV-cache pruning can reach up to 1.75 times end-to-end throughput on Apple but can reduce throughput on desktop NVIDIA GPUs. Under the common benchmark, all evaluated speculative decoding methods reduce throughput on Apple, despite reported 2-6 times gains on server GPUs. CUDA kernel designs transfer only partially: public Metal lacks asynchronous copy, and batch-one decode makes several serving-oriented mechanisms inapplicable, although transferable components yield up to 1.20 times decode throughput. Quantization gains vary by machine. Across four families, a reported speedup is not a portable property of a technique alone but a joint function of technique, runtime, hardware contract, and workload regime.

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Topics: Computer science, Porting, Parallel computing, Throughput, Speedup, Kernel (algebra)

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