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HAWC-Leak: Heterogeneous Architecture Workload Classification utilizing Side-Channel Leakage

Muhtasim Alam Chowdhury, Arthur Kim, Rozhin Yasaei, Soheil Salehi · 2026 · arXiv (Cornell University)

DOI: 10.48550/arxiv.2610.30400 · cited by 0 works (OpenAlex) · open-access PDF

Spanish

Las plataformas de computación heterogéneas de hierografía de sistemas modernos, pero confirmadas por CryNN, que integran procesadores de uso general con aceleradores especializados como FPGA, se han convertido en el estándar para aplicaciones de alto rendimiento e incorporadas. Sin embargo, los recursos físicos compartidos de estos sistemas introducen vulnerabilidades de seguridad críticas, donde los patrones de consumo de energía pueden infiltrar información de carga de trabajo sensible. Mientras que el análisis de canales laterales está bien establecido para extraer claves criptográficas de algoritmos aislados, los métodos existentes luchan por perfilar sistemas complejos y dinámicos en los que coexisten diversas cargas de trabajo en los recursos de hardware compartidos. Este documento presenta HAWC-Leak, un marco de clasificación de carga de trabajo dinámico diseñado para identificar tare

Machine translation (Meta M2M100); the English original follows.

Abstract

Modern heterogeneous computing platforms, which integrate general-purpose processors with specialized accelerators such as FPGAs, have become the standard for high-performance and embedded applications. However, the shared physical resources of these systems introduce critical security vulnerabilities, where power consumption patterns can leak sensitive runtime information. While side-channel analysis is well established for extracting cryptographic keys from isolated algorithms, existing methods struggle to profile complex, dynamic systems where diverse workloads coexist on shared hardware resources. This paper presents HAWC-Leak, a dynamic workload classification framework designed to identify specific hardware accelerator tasks in real time using non-invasive power analysis. Unlike prior studies focused on extracting cryptographic secrets from isolated implementations, our approach profiles heterogeneous runtime behavior using machine learning to predict active workloads from features extracted from power traces. We implement a complete hardware-in-the-loop measurement testbed using the ChipWhisperer CW305 Artix-7 FPGA platform to capture high-resolution power signatures of diverse workloads including Advanced Encryption Standard (AES-128), Elliptic Curve Cryptography (ECC P-256), Secure Hash Algorithm (SHA-256), Convolutional Neural Network (CNN), and a system idle state. We develop a Hierarchical Random Forest classifier that processes real-time power data to identify the executing application in controlled mixed-activity scenarios where multiple accelerators are instantiated but only one executes at a time. Experimental results demonstrate that this framework achieves 100% classification accuracy across all evaluated scenarios, confirming that power consumption patterns serve as a reliable and distinctive fingerprint for profiling heterogeneous runtime behavior.

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Topics: Computer science, Profiling (computer programming), Workload, Testbed, Cryptography, Distributed computing

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